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SUD70N02-04P

Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions SimulatedData MeasuredData Unit Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 A 1.2 V On-State Drain Currentb ID(on) VDS =5 V, VGS = 10 V 1575 A Drain-...

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SUD70N02-04P: Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions SimulatedData MeasuredData Unit Static Gate Threshold Voltage VGS(th) VDS = VGS...

SUD70N02-04P Data Sheet

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Part Number:
SUD70N02-04P
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5000

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Description



Specifications

SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Conditions Simulated
Data		 Measured
Data		 Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 A 1.2 V
On-State Drain Currentb ID(on) VDS =5 V, VGS = 10 V 1575 A
Drain-Source On-State Resistanceb rDS(on) VGS = 10V, ID = 20A 0.0028 0.0028
VGS = 10 V, ID = 20A, TJ = 125°C 0.0031
VGS = 4.5 V, ID = 20 A 0.0040 0.0047
Forward Voltageb VSD IS= 50A, VGS = 0 V 0.91 1.2 V
Dynamica
Input Capacitance Ciss VGS = 0 V, VDS = 25 V, f = 1 MHz 4503 4500 pF
Output Capacitance Coss 1550 1520
Reverse Transfer Capacitance Crss 753 800
Total Gate Chargec Qg VDS = 10 V, VGS = 4.5 V, ID =50A 37 34 nC
Gate-Source Chargec Qgs 11 11
Gate-Drain Chargec Qgd 10 10
Turn-On Delay Timec td(on) VDD = 10V, RL = 0.20
ID50A, VGEN = 10 V, RG = 2.5 		14 15 ns
Rise Timec tr 11 11
Turn-Off Delay Timec td(off) 16 35
Fall Timec tf 16 15
Source-Drain Reverse Recovery Time trr IF = 50A, di/dt = 100 A/s 31 45
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width 300 µs, duty cycle 2%.
c. Independent of operating temperature.


Description

The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model SUD70N02-04P is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance SUD70N02-04P is best fit at the gate bias near the threshold voltage.

A novel gate-to-drain feedback capacitance network of SUD70N02-04P is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values of SUD70N02-04P are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device.




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