Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions SimulatedData MeasuredData Unit Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 A 1.7 V On-State Drain Currenta ID(on) VDS = 5 V, VGS = 10 V 438 A Drain-...
SUM40N02-09P: Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions SimulatedData MeasuredData Unit Static Gate Threshold Voltage VGS(th) VDS = VGS...
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DescriptionThe SUM40N02-12P is designed as one kind of N-Channel 20V (D-S) 175°C MOSFETs with typi...
| SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) | |||||
| Parameter | Symbol | Test Conditions | Simulated Data |
Measured Data |
Unit |
| Static | |||||
| Gate Threshold Voltage | VGS(th) | VDS = VGS, ID = 250 A | 1.7 | V | |
| On-State Drain Currenta | ID(on) | VDS = 5 V, VGS = 10 V | 438 | A | |
| Drain-Source On-State Resistancea | rDS(on) | VGS = 10 V, ID = 20A | 0.0078 | 0.008 | Ω |
| VGS = 10 V, ID = 20A, TJ = 125°C | 0.010 | ||||
|
VGS = 4.5V, ID =20 A |
0.0136 | 0.0135 | |||
| Forward Voltagea | VSD | IS = 40 A, VGS = 0 V | 0.91 | 1.1 | V |
| Dynamicb | |||||
| Input Capacitance | Ciss | VGS = 0 V, VDS =10 V, f = 1 MHz | 1212 | 1300 | pF |
| Output Capacitance | Coss | 470 | 470 | ||
| Reverse Transfer Capacitance | Crss | 237 | 275 | ||
| Total Gate Chargec | Qg | VDS = 10V, VGS = 4.5 V, ID = 40 A | 10.6 | 10.5 | nC |
| Gate-Source Chargec | Qgs | 4.2 | 4.2 | ||
| Gate-Drain Chargec | Qgd | 4 | 4 | ||
| Turn-On Delay Timec | td(on) | VDD = 10 V, RL = 0.25Ω ID= 40A, VGEN = 10 V, RG = 2.5 Ω |
9 | 8 | ns |
| Rise Timec | tr | 9 | 10 | ||
| Turn-Off Delay Timec | td(off) | 32 | 25 | ||
| Fall Timec | tf | 10 | 12 | ||
| Source-Drain Reverse Recovery Time | trr | IF = 40 A, di/dt = 100 A/µs | 31 | 35 | |
The attached spice model of SUM40N02-09P describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance of SUM40N02-09P is best fit at the gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network of SUM40N02-09P is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the SUM40N02-09P.