Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions SimulatedData MeasuredData Unit Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 1.8 V On-State Drain Currenta ID(on) VDS = 5 V, VGS = 10 V 434 A ...
SUM50N03-13LC: Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions SimulatedData MeasuredData Unit Static Gate Threshold Voltage VGS(th) VDS = VGS...
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| SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) | |||||
| Parameter | Symbol | Test Conditions | Simulated Data |
Measured Data |
Unit |
| Static | |||||
| Gate Threshold Voltage | VGS(th) | VDS = VGS, ID = 250 µA | 1.8 | V | |
| On-State Drain Currenta | ID(on) | VDS = 5 V, VGS = 10 V | 434 | A | |
| Drain-Source On-State Resistancea | rDS(on) | VGS = 10 V, ID = 25 A | 0.010 | 0.010 | Ω |
| VGS = 10 V, ID = 25 A, TJ = 125°C | 0.016 | 0.016 | |||
| VGS = 10 V, ID = 25 A, TJ = 175°C | 0.018 | 0.018 | |||
| VGS = 4.5 V, ID = 24 A | 0.014 | 0.014 | |||
| Forward Voltagea | VSD | IS = 50 A, VGS = 0 V | 0.90 | 1.3 | V |
| Dynamicb | |||||
| Input Capacitance | Ciss | VGS = 0 V, VDS = 25 V, f = 1 MHz | 2009 | 1960 | pF |
| Output Capacitance | Coss | 367 | 380 | ||
| Reverse Transfer Capacitance | Crss | 111 | 180 | ||
| Total Gate Chargec | Qg | VDS = 15 V, VGS = 10 V, ID = 50 A | 34 | 35 | nC |
| Gate-Source Chargec | Qgs | 7.6 | 7.6 | ||
| Gate-Drain Chargec | Qgd | 5.6 | 5.6 | ||
| Turn-On Delay Timec | td(on) | VDD = 15 V, RL = 0.30 Ω ID = 50 A, VGEN = 10 V, RG = 2.5 Ω |
23 | 10 | ns |
| Rise Timec | tr | 19 | 93 | ||
| Turn-Off Delay Timec | td(off) | 8 | 30 | ||
| Fall Timec | tf | 10 | 10 | ||
| Reverse Recovery Time | trr | IF = 50,A di/dt = 100 A/µs | 29 | 35 | |
The attached spice SUM50N03-13LC describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network of the SUM50N03-13LC is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device.