Features: `700ps max. propagation delay`Extended 100E VEE range of 4.2V to 5.5V`Differential outputs`Fully compatible with industry standard 10KH, 100K ECL levels`Internal 75KΩ input pulldown resistors`Fully compatible with Motorola MC10E/100E150`Available in 28-pin PLCC packagePinoutDescrip...
SY100E150: Features: `700ps max. propagation delay`Extended 100E VEE range of 4.2V to 5.5V`Differential outputs`Fully compatible with industry standard 10KH, 100K ECL levels`Internal 75KΩ input pulldown ...
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DescriptionThe SY10/100E111 are low skew 1-to-9 differential drivers designed for clock distributi...

The SY10/SY100E150 are 6-bit D latches with differential outputs designed for use in new, high- performance ECL systems. When both Latch Enables (LEN1, LEN2) are at a logic LOW, the latch is in the transparent mode and input data propagates through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the input data. The Master Reset (MR) overrides all other signals to set the Q outputs to a logic LOW.