Features: `9-bit latch`Extended 100E VEE range of 4.2V to 5.5V`Parity detection/generation`800ps max. D to Output`Reset`Internal 75KΩ input pull-down resistors`Fully compatible with Motorola MC10E/100E175`Available in 28-pin PLCC packagePinoutDescriptionThe SY10/SY100E175 are 9-bit latches. ...
SY100E175: Features: `9-bit latch`Extended 100E VEE range of 4.2V to 5.5V`Parity detection/generation`800ps max. D to Output`Reset`Internal 75KΩ input pull-down resistors`Fully compatible with Motorola M...
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DescriptionThe SY10/100E111 are low skew 1-to-9 differential drivers designed for clock distributi...

The SY10/SY100E175 are 9-bit latches. They also feature a tenth latched output (ODDPAR) which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH).
The SY100E175 can also be used to generate byte parity by using D8 as the parity-type select (L = even parity, H = odd parity) and using ODDPAR as the byte parity output.
The LEN pin latches the data when asserted with a logical high and makes the latch transparent when placed at a logic low level.