SY100E336

The SY10/SY100E336 offer three bus transceivers with both transmit and receive registers and are designed for use in new, high-performance ECL systems. The bus outputs (BUS0-BUS2) are designed to drive a 25 bus. The receive outputs (Q0 Q2) are specified for 50 .The bus outputs feature a normal logic HIGH level (VOH) and a cutoff LOW level when at a logic LOW. At cutoff, the outputs go to 2.0V and the output emitter-follower is "off", presenting a high impedance to the bus. The bus outputs have edge slow-down capacitors.
The Transmit Enable pins (TEN) of SY100E336 determine whether current data is held in the transmit register or new data is loaded from the A/B inputs. A logic LOW on both of the bus enable inputs (BUSEN), when clocked through the register, disables the bus outputs to 2.0V.
The receiver section clocks bus data into the receive registers after gating with the Receive Enable (RXEN) input.
All registers of SY100E336 are clocked by rising edge of CLK1 or CLK2 (or both).
Additional grounding is provided through the ground pins (GND) which should be connected to 0V. The GND pins of SY100E336 are not electrically connected to the chip.