SY100E337

The SY10/SY100E337 are 3-bit registered bus transceivers with scan designed for use in new, high- performance ECL systems. The bus outputs (BUS0BUS2) are designed to drive a 25 bus; the receive outputs (Q0Q2) are designed for 50. The bus outputs feature a normal logic HIGH level (VOH) and a cutoff LOW level of 2.0V and the output emitter-follower is "off", presenting a high impedance to the bus. The bus outputs of SY100E337 also feature edge slow-down capacitors.
     Both drive and receive sides feature the same logic, including a loopback path to hold data. The LOAD/HOLD function is controlled by Transmit Enable (TEN) and Receive Enable (REN) on the  transmit and receive sides, respectively, with a HIGH selecting LOAD. The implementation of the SY100E337 Receive Enable differs from that of the E336.
     A synchronous bus enable (SBUSEN) is provided for  normal, non-scan operation.  The asynchronous bus disable (ABUSDIS) disables the bus for scan mode.
    The SYNCEN input of SY100E337 allows either synchronous or asynchronous re-enabling after disabling with ABUSDIS. An alternative use is asynchronous-only operation with ABUSDIS, in which caseSYNCENis tied LOW.  SYNCENis implemented as an overriding SET control to the enable flip-flop.
    Scan mode of  SY100E337 is selected by a logic HIGH at the SCAN input.  Scan input data is shifted in through S-IN, and output data appears at the Q2 output.
    All registers of SY100E337 are clocked on the rising edge of CLK.  Additional lead-frame grounding is provided through the ground pins (GND) which should be connected to 0V. The GND pins are not electrically connected to the chip.