SY100E452

Features:

`Differential D, CLK and Q
`Extended 100E V_EE range of 4.2V to 5.5V
`VBB output for single-ended use
`1100MHz min. toggle frequency
`Asynchronous Master Reset
`Fully compatible with Motorola MC10E/100E452
`Available in 28-pin PLCC package


Pinout




Description

The SY10/SY100E452 are 5-bit differential registers with differential data (inputs and outputs) and clock. The registers are triggered by a positive transition of the positive clock (CLK) input. A high on the Master Reset (MR) asynchronously resets all registers so that the Q outputs go LOW.

The differential input structures of SY100E452 are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the devices. The clamping action will assert the /D and the /CLK sides of the inputs. Because of the edge-triggered flip-flop nature of the devices, simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state.

The fully differential design of the devices makes SY100E452 ideal for very high frequency applications where a registered data path is necessary.