SY100EL29V

 3.3V and 5V power supply option
Differential D, CLK and Q
Extended V_EE range of 3.0V to 5.5V
V_BB output for single-ended use
1100MHz min. toggle frequency
Asynchronous Reset and Set
Fully compatible with Motorola MC100LVEL29 and MC100EL29
Available in 20-pin SOIC package

The SY100EL29V is a dual differential register with differential data (inputs and outputs) and clock. The registers are triggered by a positive transition of the positive clock (CLK) input. A HIGH on the Reset (Rx) asynchronously resets the appropriate register so that the Q outputs go LOW. A HIGH on the Set (Sx) asynchronously resets the appropriate register so that the Q outputs go HIGH. The Set and Reset inputs cannot both be HIGH simultaneously.

The differential input structures of SY100EL29V are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the SY100EL29V. The clamping action will assert the /D and the /CLK sides of the inputs. The noninverting input will pull down to V_EE and the inverting input will be biased around V_CC/2. Because of the edge-triggered flip-flop nature of the devices, simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state.

The fully differential design of the SY100EL29V makes them ideal for very high frequency applications where a registered data path is necessary.