Features: Guaranteed AC parameters over temp/voltage: --> 2GHz fMAX --< 25ps within-device skew --< 275ps tr/tf time -- < 525ps prop delay 2:1 Differential Mux input Flexible supply voltage: 2.5V/3.3V/5V Wide operating temperature range: 40°C to +85°C VBB reference for single-ended or ...
SY100EP14U: Features: Guaranteed AC parameters over temp/voltage: --> 2GHz fMAX --< 25ps within-device skew --< 275ps tr/tf time -- < 525ps prop delay 2:1 Differential Mux input Flexible supply volt...
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DescriptionThe SY10/100E111 are low skew 1-to-9 differential drivers designed for clock distributi...

| Symbol | Rating | Value | Unit |
| VCC VEE | Power Supply Voltage (VEE = 0) | +6.0 to 0 | V |
| VIN | Input Voltage (VCC = 0V, VIN not more negative than VEE) Input Voltage (VEE = 0V, VIN not more positive than VCC) |
-6.0 to 0 +6.0 to 0 |
V |
| IOUT | Output Current Continuous Surge |
50 100 |
mA |
| IBB | VBB Sink/Source Current(2) | ±0.5 | mA |
| TA | Operating Temperature Range | -40 to +85 | °C |
| TSTORE | Storage Temperature Range | -65 to +150 | °C |
| ESD | Mil Std. 883 Human Body Model, All Pins | >1.5k | V |
| JA | Thermal Resistance (Junction-to-Ambient) Still Air 500lfp |
160 109 |
°C/W |
| JC | Thermal Resistance (Junction-to-Case) | 39 | °C/W |
The SY100EP14U is a high-speed, 2GHz differential PECL/ECL 1:5 fanout buffer optimized for ultra-low skew applications. Within device skew is guaranteed to be less than 25ps over temperature and supply voltage. The wide supply voltage operation allows this fanout buffer to operate in 2.5V, 3.3V, and 5V systems. A VBB reference is included for single-supply or AC-coupled PECL/ECL input applications, thus eliminating resistor networks. When interfacing to a single-ended or AC-coupled PECL/ECL input signal, connect the VBB pin to the unused /CLK pin, and bypass the pin to VCC through a 0.01F capacitor.
The SY100EP14U features a 2:1 input MUX, making it an ideal solution for redundant clock switchover applications. If only one input pair is used, the other pair may be left floating. In addition, this device includes a synchronous enable pin that forces the outputs into a fixed logic state. Enable or disable state is initiated only after the outputs are in a LOW state, thus eliminating the possibility of a "runt" clock pulse.
The SY100EP14U I/O are fully differential and 100K ECL compatible. Differential 10K ECL logic can interface directly into the SY100EP14U inputs.
The SY100EP14U is part of Micrel's high-speed clock synchronization family. For applications that require a different I/O combination, consult the Micrel website at www.micrel.com, and choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators, and clock generators.