SY100EP195V

SY100EP195V is a programmable delay line, varying the delay of a PECL or NECL input signal by any amount between about 2.2ns and 12.2ns. A 10-bit digital control register affords delay steps of approximately 10ps.

SY100EP195V implements the delay using a multiplexer chain and a set of fixed delay elements. Under digital control, various subsets of the delay elements are included in the signal chain. To simplify interfacing, the 10-bit digital delay control word interfaces to PECL, CMOS, or TTL interface standards.

Since multiplexers must appear in the delay path, SY100EP195V has a minimum delay of about 2.2ns. Delays below this value are not possible. In addition, when cascading multiple SY100EP195V to extend the delay range, the minimum delay is about 2.2ns times the number of SY100EP195V in cascade. An eleventh control bit, D[10], along with the CASCADE and /CASCADE outputs and the SETMIN and SETMAX inputs, simplifies the task of cascading