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SY100EPT21L

Features: · 3.3V power supply· 1.9ns typical propagation delay· 275MHz fMAX (Clock bit stream, not pseudo-random)· Differential LVPECL inputs· 24mA LVTTL outputs· Flow-through pinouts· Internal input resistors: pulldown on D, pulldown and pullup on /D· Q output will default LOW with inputs open or...

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SeekIC No. : 004509958 Detail

SY100EPT21L: Features: · 3.3V power supply· 1.9ns typical propagation delay· 275MHz fMAX (Clock bit stream, not pseudo-random)· Differential LVPECL inputs· 24mA LVTTL outputs· Flow-through pinouts· Internal inpu...

SY100EPT21L Data Sheet

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Part Number:
SY100EPT21L
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· 3.3V power supply
· 1.9ns typical propagation delay
· 275MHz fMAX (Clock bit stream, not pseudo-random)
· Differential LVPECL inputs
· 24mA LVTTL outputs
· Flow-through pinouts
· Internal input resistors: pulldown on D, pulldown and pullup on /D
· Q output will default LOW with inputs open or at GND
· VBB output
· Available in 8-pin MSOP and SOIC package


Pinout

Connection Diagram


Specifications

Symbol
Paramter
Value
Unit
VCC
 Power Supply Voltage
0.5 to +3.8
V
VI
 PECL Input Voltage
0V to VCC+0.5
V
VO
 Voltage Applied to
Output at HIGH State
0.5 to VCC
V
IO Current Applied to
Output at LOW State
Twice the Rated IOL
mA
Tstore
 Storage Temperature
65 to +150
TA
 Operating Temperature
40 to +85



Description

The SY100EPT21L is a single differential LVPECL-to- LVTTL translator using a single +3.3V power supply.  Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3V and ground are required. The small outline 8-lead SOIC package and low skew single gate design make the SY100EPT21L ideal for applications that require the translation of a clock or data signal where minimal space, low power, and low cost are critical.

VBB allows a differential, single-ended, or AC-coupled interface to the device. If used, the VBB output of SY100EPT21L should be bypassed to VCC with 0.01F capacitor.

Under open input conditions, the /D will be biased at a VCC/2 voltage level and the D input will be pulled to ground. This condition of SY100EPT21L will force the Q output low to provide added stability.

The SY100EPT21L is compatible with positive ECL 100K logic levels.




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