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SY100H641

Features: *Input frequencies up to 135MHz* PECL-to-TTL version of popular ECLinPS E111* Guaranteed low skew specification* Latched input* Differential internal design* VBB output VECL for single-ended operation* Single +5V supply* Reset/enable* Extra TTL and ECL power/ground pins*Choice of ECL com...

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SY100H641: Features: *Input frequencies up to 135MHz* PECL-to-TTL version of popular ECLinPS E111* Guaranteed low skew specification* Latched input* Differential internal design* VBB output VECL for single-end...

SY100H641 Data Sheet

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Part Number:
SY100H641
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/23

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Product Details

Description



Features:

* Input frequencies up to 135MHz
* PECL-to-TTL version of popular ECLinPS E111
*  Guaranteed low skew specification
*  Latched input
*  Differential internal design
* VBB output VECL for single-ended operation
*  Single +5V supply
*  Reset/enable
*  Extra TTL and ECL power/ground pins
* Choice of ECL compatibility: MECL 10KH (10Hxxx)
   or 100K (100Hxxx)
* Available in 28-pin PLCC package


Pinout

Connection Diagram


Specifications

Symbol Rating Value Unit
VE (ECL)
VT (TTL)		 Power Supply
Voltage
 0.5 to +7.0
0.5 to +7.0		 V
VI (ECL) Input Voltage 0.0 to VEE V
VOUT (TTL) Disabled 3-State
Output		 0.0 to VCCT V
IOUT (ECL) Output Current
- Continuous
- Surge		 50
100		 mA
Tstore Storage Temperature 65 to +150 °C
TA Operating Temperature 0 to +85 °C



Description

The SY10/SY100H641 are single supply, low skew translating 1:9 clock drivers. Devices in the Micrel- Synergy H600 translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical performance.

The SY100H641 feature a 24mA TTL output stage with AC performance specified into a 50pF load capacitance. A latch is provided on-chip. When LEN is LOW (or left open, in which case it is pulled LOW by the internal pulldowns), the latch is transparent. A HIGH on the enable pin (EN) forces all outputs LOW.

The SY100H641 version is compatible with MECL 10KH ECL logic levels. The 100H version is compatible with 100K levels.




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