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SY100H841L

Features: · 3.3V power supply·Translates positive ECL to TTL (PECL-to-TTL)· 300ps pin-to-pin skew· 500ps part-to-part skew· Differential internal design for increased noise immunity and stable threshold inputs· VBB reference output·Single supply· Enable input· Latch enable input· Extra TTL and ECL...

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SeekIC No. : 004509970 Detail

SY100H841L: Features: · 3.3V power supply·Translates positive ECL to TTL (PECL-to-TTL)· 300ps pin-to-pin skew· 500ps part-to-part skew· Differential internal design for increased noise immunity and stable thres...

SY100H841L Data Sheet

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Part Number:
SY100H841L
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· 3.3V power supply
·Translates positive ECL to TTL (PECL-to-TTL)
· 300ps pin-to-pin skew
· 500ps part-to-part skew
· Differential internal design for increased noise immunity and stable threshold inputs
· VBB reference output
· Single supply
· Enable input
· Latch enable input
· Extra TTL and ECL power/ground pins to reduce cross-talk/noise
· High drive capability: 24mA each output
· Fully compatible with industry standard 10K, 100K I/O levels
· Available in 16-pin SOIC package


Pinout

Connection Diagram


Specifications

Symbol Rating Value Unit
V E (ECL)
V T (TTL)		 Power Supply
Voltage		 0.5 to +7.0
0.5 to +7.0		 V
V I (ECL)
V OUT (TTL)		 Input Voltage 0.0 to V EE
0.0 to V T		 V
Tstore Storage Temperature 65 to +150
TA Operating Temperature 0 to +85


NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability.




Description

The SY10/SY100H841L are single supply, low skew translating 1:4 clock drivers.

The SY100H841L feature a 24mA TTL output stage, with AC performance specified into a 20pF load capacitance.

A latch is provided on-chip. When LEN is LOW (or left open, in which case SY100H841L is pulled low by the internal pulldowns) the latch is transparent. A HIGH on the enable pin (EN) forces all outputs LOW.

As frequencies increase to 40MHz and above, precise timing and shaping of clock signals becomes extremely important. The SY100H841L solves several clock distribution problems such as minimizing skew (300ps), maximizing clock fanout (24mA drive), and precise duty cycle control through a proprietary differential internal design.

The 10K version is compatible with 10KH ECL logic levels. The SY100H841L version is compatible with 100K levels.




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