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SY100S324

Features: `Max. propagation delay of 1.4ns`IEE min. of 70mA`Industry standard 100K ECL levels`Extended supply voltage option: VEE = 4.2V to 5.5V`Differential outputs`Voltage and temperature compensation for improved noise immunity`Internal 75KΩ input pull-down resistors`Twice as fast as Fair...

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SY100S324: Features: `Max. propagation delay of 1.4ns`IEE min. of 70mA`Industry standard 100K ECL levels`Extended supply voltage option: VEE = 4.2V to 5.5V`Differential outputs`Voltage and temperature compensa...

SY100S324 Data Sheet

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Part Number:
SY100S324
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/23

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Product Details

Description



Features:

`Max. propagation delay of 1.4ns
`IEE min. of 70mA
`Industry standard 100K ECL levels
`Extended supply voltage option: VEE = 4.2V to 5.5V
`Differential outputs
`Voltage and temperature compensation for improved noise immunity
`Internal 75KΩ input pull-down resistors
`Twice as fast as Fairchild's 324
`Function and pinout compatible with Fairchild F100K
`Available in 24-pin CERPACK and 28-pin PLCC packages




Pinout

Connection Diagram




Description

The SY100S324 is a hex translator designed to convert TTL logic levels to 100K ECL levels. The inputs are TTL compatible with differential outputs that can either be used as an inverting/non-inverting translator or as differential line drivers. A common Enable (E), when LOW, holds all inverting outputs HIGH and holds all noninverting outputs LOW.

When used in the differential mode, due to its high common mode rejection, SY100S324's overcomes voltage gradients between the TTL and ECL ground systems. The VEE and VTTL power may be applied in either order.






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