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SY100S341

Features: `Max. shift frequency of 600MHz`Max. Clock to Q delay of 1200ps`IEE min. of 150mA`Industry standard 100K ECL levels`Extended supply voltage option: VEE = 4.2V to 5.5V`Voltage and temperature compensation for improved noise immunity`Internal 75KΩ input pull-down resistors`70% faster...

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SeekIC No. : 004509989 Detail

SY100S341: Features: `Max. shift frequency of 600MHz`Max. Clock to Q delay of 1200ps`IEE min. of 150mA`Industry standard 100K ECL levels`Extended supply voltage option: VEE = 4.2V to 5.5V`Voltage and temperatu...

SY100S341 Data Sheet

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Part Number:
SY100S341
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/23

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Product Details

Description



Features:

`Max. shift frequency of 600MHz
`Max. Clock to Q delay of 1200ps
`IEE min. of 150mA
`Industry standard 100K ECL levels
`Extended supply voltage option: VEE = 4.2V to 5.5V
`Voltage and temperature compensation for improved noise immunity
`Internal 75KΩ input pull-down resistors
`70% faster than Fairchild 300K at lower power
`Function and pinout compatible with Fairchild F100K
`Available in 24-pin CERPACK and 28-pin PLCC packages


Pinout

Connection Diagram


Description

The SY100S341 offer eight D-type, edge-triggered flipflops with both individual inputs for parallel operation as well as serial inputs for bidirectional shifting, and are designed for use in high-performance ECL systems. Data is clocked into the flip-flops on the rising edge of the clock.

The mode of operation is selected by two Select inputs (S0, S1) which determine if the SY100S341 performs a shift, hold or parallel entry function, as described in the Truth Table. The inputs on these devices have 75KΩ pull-down resistors.




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