SY100S360

The SY100S360 is a dual parity checker/generator and is designed for use in high-performance ECL systems. The inputs are segmented into two groups of nine inputs each and the parity output is at a logic LOW when an even number of inputs are at a logic HIGH. In each group, one of the nine inputs (Ia, Ib) has a shorter propagation delay and, therefore, is ideal as the expansion input for parity generation of wider data.

A Compare output (C) of SY100S360 is also provided which allows comparison of two 8-bit words. A logic LOW on the C output indicates a match. The inputs on this device have 75KΩ pull-down resistors.