SY100S364

Features:

Max. propagation delay of 1300ps
IEE min. of 63mA
Industry standard 100K ECL levels
Extended supply voltage option:
VEE = 4.2V to 5.5V
Voltage and temperature compensation for improved noise immunity
Internal 75KΩ input pull-down resistors
70% faster than Fairchild
40% lower power than Fairchild
Function and pinout compatible with Fairchild F100K
Available in 24-pin CERPACK and 28-pin PLCC packages




Pinout






Description

The SY100S364 is a 16-input multiplexer designed for use in high-performance ECL systems. The four Data Select inputs (S0, S1, S2, S3) determine the bit from the 16 inputs (In) that will be passed on to the output as shown inthe Truth Table. The output data polarity is the same as the input. The inputs on the device have 75KΩpulldownresistors.