SY100S839V

The SY100S839V is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL/LVECL or, if positive power supplies are used, PECL/LVPECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC-coupled into the device. If a singleended input is to be used, the VBB output should be connected to the /CLK input and bypassed to ground via a 0.01F capacitor. The VBB output is designed to act as the switching reference for the input of the S839V under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current.

The common enable (/EN) of SY100S839V is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the SY100S839V is enabled/disabled as ca happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.

Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one SY100S839V, the MR pin need not be exercised as the internal divider designs ensures synchronization between the ÷2/4, and the ÷4/5/6 outputs of a single device.