SY100S891

The SY100S891 is a 5-bit registered transceiver containing five bus transceivers with both transmit and receive registers. The bus outputs (BUS0 BUS4) are specified for driving a 25 ohm bus and the receive outputs (Q0 Q4) are specified for driving a 50 ohm line. The bus outputs have a normal high level output voltage and a normal low level output voltage when the bus enable (BUSEN0 BUSEN4) is high. However, the output of SY100S891 is switched to a cut-off level when a bus-enable is low.

This cut-off level of SY100S891 is sufficiently low that a relatively high impedance is presented to the bus in order to minimize reflections. There is one bus-enable for each bus driver; a clock (CLK1) which is common to all five bus driver registers; and a separate clock (CLK2) which is common to all five receive registers. Data at the D inputs is clocked to the Bus register by a positive transition of CLK1 and data on the bus is clocked into the Receiver register by a positive transition of CLK2. A high on the Master Reset clears all registers.