SY10E137

The SY10E137/100E137 are very high speed binary ripple counters. The two least significant bits were designed with very fast edge rates, while the more significant bits maintain standard ECLinPS output edge rates. This allows the counters to operate at very high frequencies, while maintaining a moderate power dissipation level.

The SY10E137 is ideally suited for multiple frequency clock generation, as well as for counters in highperformance ATE time measurement boards.

Both asynchronous and synchronous enables are available to maximize the SY10E137's flexibility for various applications. The asynchronous enable input, A_Start, when asserted, enables the counter while overriding any synchronous enable signals. The SY10E137 features XOR'ed enable inputs, EN1 and EN2, which are synchronous to the CLK input. When only one synchronous enable is asserted, the counter becomes disabled on the next CLK transition. All outputs of SY10E137 remain in the previous state poised for the other synchronous enable or A_Start to be asserted in order to re-enable the counter. Asserting both synchronous enables causes the counter to become enabled on the next transition of the CLK. EN1 (or EN2) and CLK edges are coincident. Sufficient delay has been inserted in the CLK path (to compensate for the XOR gate delay and the internal D-flip-flop set-up time) to ensure that the synchronous enable signal is clocked correctly; hence, the counter is disabled.

The SY10E137 can also be driven single-endedly utilizing the VBB output supply as the voltage reference for the CLK input signal. If a single-ended signal is to be used, the VBB pin should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. VBB can only source/sink 0.5mA; therefore, it should be used as a switching reference for the SY10E137 only.

All input pins of SY10E137left open will be pulled LOW via an input pull-down resistor. Therefore, do not leave the differential CLK inputs open. Doing so causes the current source transistor of the input clock gate to become saturated, thus upsetting the internal bias regulators and jeopardizing the stability of the device.

The asynchronous Master Reset resets the counter to an all zero state upon assertion.