SY10E143

The SY10E143/100E143 are high-speed 9-bit hold registers designed for use in new, high-performance ECL systems. The SY10E143 can hold current data or load new data. The nine inputs, D0-D8, accept parallel input data.

The SEL (Select) control pin serves to determine the mode of operation; either HOLD or LOAD. The input data of SY10E143 has to meet the set-up time before being clocked into the nine input registers on the rising edge of CLK1 or CLK2. The MR (Master Reset) control signal asynchronously resets all nine registers to a logic LOW when a logic HIGH is applied to MR.

The SY10E143 is designed for applications requiring highspeed registers, pipeline registers, synchronous operation, and is also suitable for byte-wide parity.