SY10E195

The SY10E195/100E195 are programmable delay chips (PDCs) designed primarily for clock de-skewing and timing adjustment. They provide variable delay of a differential ECL input transition.

The delay section consists of a chain of gates organized as shown in the logic diagram. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80ps. These two elements provide the SY10E195 with a digitally-selectable resolution of approximately 20ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on-chip by a high signal on the latch enable (LEN) control. If the LEN signal is either LOW or left floating, then the latch is transparent.

Because the delay programmability of the SY10E195 is achieved by purely differential ECL gate delays, the device will operate at frequencies of >1GHz, while maintaining over 600mV of output swing.

The SY10E195 thus offers very fine resolution, at very high frequencies, selectable entirely from a digital input, allowing for very accurate system clock timing.

An eighth latched input, D7, is provided for cascading multiple PDCs for increased programmable range. The cascade logic of SY10E195 allows full control of multiple PDCs, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating.