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SY10ELT21

Features: 2.5ns typical propagation delay Low power Differential PECL inputs 24mA TTL outputs Flow-through pinouts Available in 8-pin SOIC packagePinoutSpecifications Symbol Parameter Value Unit VCC Power Supply Voltage 0.5 to +7.0 V VI PECL Input Voltage 0V to VCC+0.5 V VO ...

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SeekIC No. : 004510081 Detail

SY10ELT21: Features: 2.5ns typical propagation delay Low power Differential PECL inputs 24mA TTL outputs Flow-through pinouts Available in 8-pin SOIC packagePinoutSpecifications Symbol Parameter Value ...

SY10ELT21 Data Sheet

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Part Number:
SY10ELT21
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/23

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Product Details

Description



Features:

 2.5ns typical propagation delay
Low power
Differential PECL inputs
24mA TTL outputs
Flow-through pinouts
Available in 8-pin SOIC package


Pinout

Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC Power Supply Voltage 0.5 to +7.0 V
VI PECL Input Voltage 0V to VCC+0.5 V
VO Voltage Applied to Output at HIGH State 0.5 to +5.5 V
IO Current Applied to
Output at LOW State		 Twice the
Rated IOL		 mA
Tstore Storage Temperature 65 to +150 °C
TA Operating Temperature 40 to +85 °C



Description

The SY10ELT21/100ELT21 are single differential PECL-to- TTL translators. Because PECL (Positive ECL) levels are used, only +5V and ground are required. The small outline 8-lead SOIC package and low skew single gate design make the SY10ELT21 ideal for applications that require the translation of a clock or data signal where minimal space, low power, and low cost are critical.
 
The VBB output allow differential single-ended, or ACcoupled interface to the device. If used, the VBB output of SY10ELT21 should be bypassed to VCC with a 0.01F capacitor.

The SY10ELT21 is available in both ECL standards: the 10ELT is compatible with positive ECL 10H logic levels, while the 100ELT is compatible with positive ECL 100K logic levels.




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