Features: 3.3V power supply 2.0ns typical propagation delay Low power Differential LVPECL inputs 24mA TTL outputs Flow-through pinouts Available in 8-pin SOIC packagePinoutSpecifications Symbol Parameter Value Unit VCC Power Supply Voltage 0.5 to +7.0 V VI PECL Input Voltage 0V...
SY10ELT21L: Features: 3.3V power supply 2.0ns typical propagation delay Low power Differential LVPECL inputs 24mA TTL outputs Flow-through pinouts Available in 8-pin SOIC packagePinoutSpecifications Symbo...
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DescriptionThe SY10/100E111 are low skew 1-to-9 differential drivers designed for clock distributi...

| Symbol | Parameter | Value | Unit |
| VCC | Power Supply Voltage | 0.5 to +7.0 | V |
| VI | PECL Input Voltage | 0V to VCC+0.5 | V |
| VO | Voltage Applied to Output at HIGH State | 0.5 to +5.5 | V |
| IO | Current Applied to Output at LOW State |
Twice the Rated IOL |
mA |
| Tstore | Storage Temperature | 65 to +150 | °C |
| TA | Operating Temperature | 40 to +85 | °C |
The SY10ELT21L/100ELT21L are single differential LVPECLto- LVTTL translators using a single +3.3V power supply. Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3V and ground are required. The small outline 8-lead SOIC package and low skew single gate design make the ELT21L ideal for applications that require the translation of a clock or data signal where minimal space, low power, and low cost are critical.
VBB allows a differential, single-ended, SY10ELT21L, or AC-coupled interface to the device. If used, the VBB output should be bypassed to VCC with 0.01F capacitor.
Under open input conditions, the /D will be biased at a VCC/2 voltage level and the D input will be pulled to ground. This condition will force the Q output low to provide added stability.
The ELT21L is available in both ECL standards: the SY10ELT21L is compatible with positive ECL 10H logic levels, while the 100ELT is compatible with positive ECL 100K logic levels.