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SY10H842

Features: · Translates positive ECL-to-TTL (PECL-to-TTL)· 300ps pin-to-pin skew· 500ps part-to-part skew· Differential internal design for increased noise immunity and stable threshold inputs· VBB reference output· Single supply· Enable input· Extra TTL and ECL power/ground pins to reduce cross-ta...

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SeekIC No. : 004510111 Detail

SY10H842: Features: · Translates positive ECL-to-TTL (PECL-to-TTL)· 300ps pin-to-pin skew· 500ps part-to-part skew· Differential internal design for increased noise immunity and stable threshold inputs· VBB r...

SY10H842 Data Sheet

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Part Number:
SY10H842
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· Translates positive ECL-to-TTL (PECL-to-TTL)
· 300ps pin-to-pin skew
· 500ps part-to-part skew
· Differential internal design for increased noise immunity and stable threshold inputs
· VBB reference output
· Single supply
· Enable input
· Extra TTL and ECL power/ground pins to reduce cross-talk/noise
· High drive capability: 24mA each output
· Fully compatible with industry standard 10K, 100K I/O levels
· Available in 16-pin SOIC package


Pinout

Connection Diagram


Specifications

Symbol Rating Value UNIT
V E (ECL) Power Supply 0.5 to +7.0 V
 V T (TTL) Voltage 0.5 to +7.0 V
V I (ECL) Input Voltage 0.0 to VEE V
V OUT (TTL) 0.0 to VT V
Tstore Storage Temperature 65 to +150
TA Operating Temperature 0 to +85

NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability.




Description

The SY10H842/100H842 are single supply, low skew translating 1:4 clock drivers.

The SY10H842 feature a 24mA TTL output stage, with AC performance specified into a 50pF load capacitance. A HIGH on the enable pin (EN) forces all outputs LOW.

As frequencies increase to 40MHz and above, precise timing and shaping of clock signals becomes extremely important. The SY10H842 solves several clock distribution  problems such as minimizing skew 300ps), maximizing clock fanout (24mA drive), and precise duty cycle control through a proprietary differential internal design.

The SY10H842 version is compatible with 10KH ECL logic levels. The 100K version is compatible with 100K levels.




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