DescriptionThe SY10/100ELT20V is a single TTL-to-differential PECL translator. Because PECL (Positive ECL) levels are used, either +5V or +3.3V and ground are required. The small outline 8-lead SOIC package and low skew single gate design make the SY10/100ELT20V ideal for applications that require...
SY10/100ELT20V: DescriptionThe SY10/100ELT20V is a single TTL-to-differential PECL translator. Because PECL (Positive ECL) levels are used, either +5V or +3.3V and ground are required. The small outline 8-lead SOIC...
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DescriptionThe SY10/100E111 are low skew 1-to-9 differential drivers designed for clock distributi...
The SY10/100ELT20V is a single TTL-to-differential PECL translator. Because PECL (Positive ECL) levels are used, either +5V or +3.3V and ground are required. The small outline 8-lead SOIC package and low skew single gate design make the SY10/100ELT20V ideal for applications that require the translation of a clock or data signal where minimal space, low power, and low cost are critical.
The SY10/100ELT20V is available in both ECL standards: the 10ELT is compatible with positive ECL 10H logic levels, while the 100ELT is compatible with positive ECL 100K logic levels.