SY89809L

The SY89809L is a High-Performance Bus Clock Driver with 9 differential HSTL (High-Speed Transceiver Logic) output pairs. The part is designed for use in low-voltage (3.3V/1.8V) applications which require a large number of outputs to drive precisely aligned, ultralow skew signals to their destination. The input is multiplexed from either HSTL or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic) by the CLK_SEL pin. The Output Enable (OE) is synchronous so that the outputs will only be enabled/ disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.

The SY89809L features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max.)-performance previously unachievable in a standard product having such a high number of outputs. The SY89809L is available in a single space saving package, enabling a lower overall cost solution.