Position: Home  > All Categories> Integrated Circuits (ICs) > SY89871U

SY89871U

Features: Two matched-delay outputs:Bank A: undivided pass-through (QA)Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1) Matched delay: all outputs have matched delay, independent of divider setting Guaranteed AC performance:>2.5GHz fMAX<250ps tr/tf<670ps tpd (matched delay)<15ps w...

product image

SY89871U Picture
See larger image
SeekIC No. : 004510398 Detail

SY89871U: Features: Two matched-delay outputs:Bank A: undivided pass-through (QA)Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1) Matched delay: all outputs have matched delay, independent of divider set...

SY89871U Data Sheet

floor Price/Ceiling Price

Get Latest Price
Part Number:
SY89871U
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2025/12/23

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

Two matched-delay outputs:
Bank A: undivided pass-through (QA)
Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1)
Matched delay: all outputs have matched delay, independent of divider setting
Guaranteed AC performance:
>2.5GHz fMAX
<250ps tr/tf
<670ps tpd (matched delay)
<15ps within-device skew
Low jitter design
<1psrms cycle-to-cycle jitter
<10pspp total jitter
Power supply 3.3V or 2.5V
Unique patent-pending input termination and VT pin for DC-coupled and AC-coupled inputs:
any differential inputs (LVPECL, LVDS, CML, HSTL)
TTL/CMOS inputs for select and reset
100K EP compatible LVPECL outputs
Parallel programming capability
Wide operating temperature range: 40°C to +85°C
Available in 16-pin (3mm * 3mm) MLF™ package




Application

OC-3 to OC-192 SONET/SDH applications
Transponders
Oscillators
SONET/SDH line cards




Pinout

Connection Diagram




Specifications

Supply Voltage (VCC) ............................... 0.5V to +4.0V
Input Voltage (VIN) ........................... 0.5V to VCC +0.3V
PECL Output Current (IOUT)
Continuous .........................................................50mA
Surge ................................................................100mA
VT Current (IVT) ...................................................±100mA
Input Current IN, /IN (IIN) ..................................... ±50mA
VREF-AC Sink/Source Current (IVREF-AC)(3) .............. ±2mA
Lead Temperature (soldering, 10 sec.) .................. 220°C
Storage Temperature (TS) .................. 65°C to +150°C
3. Due to the limited drive capability use for input of the same package only.




Description

The SY89871U is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency-locked lower speed version of the input clock (Bank B). Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components.

The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the SY89871U to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications.

The SY89871U includes two phase-matched output banks. Bank A (QA) is a frequency-matched copy of the input. Bank B (QB0, QB1) is a divided down output of the input frequency. Bank A and Bank B maintain a matched delay independent of the divider setting.






Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.