Si5364

Note: Permanent device damage can occur if the Absolute Maximum Ratings are exceeded. Restrict functional  peration to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods might affect device reliability.

The Si5364 is a complete solution for ultra-low jitter high-speed clock generation and distribution in precision clocking applications, such as OC-192/OC-48 SONET/SDH line/port cards. This device phase locks to one of three reference inputs of the Si5364 in the range of 19.44 MHz and generates four synchronous clock outputs that can be independently configured for operation in the 19, 155, or 622 MHz range (1, 8, and 32x input clock).Silicon Laboratories DSPLL™ technology delivers phase-locked loop (PLL) functionality with unparalleled performance while eliminating external loop filter components,providing programmable loop parameters, and simplifying design. The on-chip reference monitoring and clock switching functions support Stratum 3/3E and SMC compatible clock switching with excellent output phase transient characteristics. FEC rates are supported with selectable 255/238 or 238/255 scaling of the clock multiplication ratios.The Si5364 establishes a new standard in performance and integration for ultra-low jitter clock generation. It operates from a single 3.3 V supply.