SiI141B

Features: • Scaleable Bandwidth: 25-86 MHz (VGA to High Refresh XGA)• Low Power: 3.3V core operation & power-down mode• Automatic power down when clock is inactive• High Skew Tolerance: 1 full input clock cycle (15ns at 65 MHz)• Pin-compatible with SiI 101, SiI 14...

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SiI141B Picture
SeekIC No. : 004491222 Detail

SiI141B: Features: • Scaleable Bandwidth: 25-86 MHz (VGA to High Refresh XGA)• Low Power: 3.3V core operation & power-down mode• Automatic power down when clock is inactive• High ...

floor Price/Ceiling Price

Part Number:
SiI141B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/19

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Product Details

Description



Features:

• Scaleable Bandwidth: 25-86 MHz (VGA to High Refresh XGA)
• Low Power: 3.3V core operation & power-down mode
• Automatic power down when clock is inactive
• High Skew Tolerance: 1 full input clock cycle (15ns at 65 MHz)
• Pin-compatible with SiI 101, SiI 141
• Sync Detect: for Plug & Display "Hot Plugging"
• Cable Distance Support: over 5m with twisted-pair, fiber-optics ready
• Compliant with DVI 1.0 (DVI is backwards compatible with VESA® P&DTM and DFP)



Pinout

  Connection Diagram


Specifications

Note: Permanent device damage may occur if absolute maximum conditions are exceeded. Functional operation should be restricted to the conditions described under Normal Operating Conditions.

Symbol
Parameter
Min
Typ
Max
Units
VCC
Supply Voltage 3.3V
-0.3
4.0
V
VI
Input Voltage
-0.3
VCC+ 0.3
V
VO
Output Voltage
-0.3
VCC+ 0.3
V
TA
Ambient Temperature (with power applied)
-25
105
TSTG
Storage Temperature
-40
150
JA
Thermal Resistance (Junction to Ambient)
45
/W



Description

The SiI141B uses PanelLink Digital technology to support displays ranging from VGA to High Refresh XGA (25-86 MHz), which is ideal for LCD desktop monitor applications. With a flexible single or dual pixel out interface and selectable output drive, the SiI 141B receiver supports up to true color panels (24 bit/pixel, 16.7M colors) in 1 pixel/clock mode (18 bit/pixel in 2 pixel/clock mode). PanelLink also features an inter-pair skew tolerance up to 1 full input clock cycle. The SiI141B is pin for pin compatible with the SiI 141 but incorporates a number of enhancements. These include an improved jitter tolerant PLL design, new HSYNC filter and power down when the clock is inactive. All PanelLink products are designed on a scaleable CMOS architecture to support future performance requirements while maintaining the same logical interface. System designers can be assured that the interface will be fixed through a number of technology and performance generations.

The SiI141B's provider PanelLink Digital technology simplifies PC design by resolving many of the system level issues associated with high-speed digital design, providing the system designer with a digital interface solution that is quicker to market and lower in cost




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