TC520A

Features:

Converts TC500/TC500A/TC510/TC514 to Serial
Operation
Programmable Conversion Rate and Resolution fo
Maximum Flexibility
Supports up to 17-Bits of Accuracy Plus Polarity B
Low Power Operation: Typically 7.5m?
14-Pin PDIP or 16-Pin SOIC Packages
Polled or Interrupt Mode Operation




Application

Computer Peripheral Interface
Portable Instruments
Data Acquisition System Interface




Pinout






Specifications

Parameter Name	Value
Input Voltage Range (V)	Vss + 1.5 to Vdd - 1.5
Sampling Rate	4 to 10
Programmable resolution/conversion time	No
Input Channels	0
Charge pump (-V) output pin	No
Resolution	Up to 17 bits
Sampling Rate (Conv/sec)	4 to 10
Interface	Serial Port
Supply Voltage Min (V)	4.5
Supply Voltage Max (V)	5.5

Parameter NameValueInput Voltage Range (V)Vss + 1.5 to Vdd - 1.5Sampling Rate4 to 10Programmable resolution/conversion timeNoInput Channels0Charge pump (-V) output pinNoResolutionUp to 17 bitsSampling Rate (Conv/sec)4 to 10InterfaceSerial PortSupply Voltage Min (V)4.5Supply Voltage Max (V)5.5

DC Supply Voltage (V _DD)....................................+6.0V
Input Voltage (All Inputs V _IN):.... - 0.3V to (V_DD+0.3V)
Operating Temperature Range (T _A)..........0 to 70
Storage Temperature Range..............-65 to +150




Description

The TC520A Serial Interface Adapter provides logic control for Microchip's TC500/500A/510/514 family of dual slope,integratingA/Dconverters. ItdirectlymanagesTC500 converter phase control signals A, B, and CMPTR thereby reducing host processor task loading and software complexity. Communication with the TC520A is accomplished over a 3wire serial port. Key converter operating parameters are programmable for complete user flexibility. Data conversion initiated when the CE input is brought low. The converted data (plus overrange and polarity bits) are held in an 18 bit shift register until read by the processor, or until the next conversion is completed. Data may be clocked out of the TC520A at any time, and at any rate the user prefers. A Data Valid (DV) output is driven active at the start of each conversion cycle indicating the 18 bit shift register update has just been completed. This signal may be polled by the processor, or can be used as data ready interrupt. The TC520A timebase can be derived from an external frequency source of up to 6MHz; or can operate from its own external crystal. It requires a single 5V logic supply and dissipates less than 7.5mW.