TC59SMAFTL-70

Features: • Single power supply of 3.3 V ± 0.3 V• Up to 143 MHz clock frequency• Synchronous operations: All signals referenced to the positive edges of clock• Architecture: Pipeline• Organization TC59SM716AFT/AFTL: 2,097,152 words × 4 banks × 16 bits TC59SM708AFT/AFT...

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TC59SMAFTL-70 Picture
SeekIC No. : 004514243 Detail

TC59SMAFTL-70: Features: • Single power supply of 3.3 V ± 0.3 V• Up to 143 MHz clock frequency• Synchronous operations: All signals referenced to the positive edges of clock• Architecture: ...

floor Price/Ceiling Price

Part Number:
TC59SMAFTL-70
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/17

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Product Details

Description



Features:

• Single power supply of 3.3 V ± 0.3 V
• Up to 143 MHz clock frequency
• Synchronous operations: All signals referenced to the positive edges of clock
• Architecture: Pipeline
• Organization
   TC59SM716AFT/AFTL: 2,097,152 words × 4 banks × 16 bits
   TC59SM708AFT/AFTL: 4,194,304 words × 4 banks × 8 bits
   TC59SM704AFT/AFTL: 8,388,608 words × 4 banks × 4 bits
• Programmable Mode register
• Auto Refresh and Self Refresh
• Burst Length: 1, 2, 4, 8, Full page
• CAS Latency: 2, 3
• Single Write Mode
• Burst Stop Function
• Byte Data Controlled by L-DQM, U-DQM (TC59SM716)
• 4K Refresh cycles/64 ms
• Interface: LVTTL
• Package
   TC59SM716AFT/AFTL: TSOPII54-P-400-0.80B
   TC59SM708AFT/AFTL: TSOPII54-P-400-0.80B
   TC59SM704AFT/AFTL: TSOPII54-P-400-0.80B



Pinout

  Connection Diagram




Specifications

SYMBOL
PARAMETER
RATING
UNIT
NOTES
VIN, VOUT
Input, Output Voltage
−0.3~VCC + 0.3
V
1
VCC, VCCQ
Power Supply Voltage
−0.3~4.6
V
1
Topr
Operating Temperature
0~70
1
Tstg
Storage Temperature
−55~150
1
Tsolder
Soldering Temperature (10s)
260
1
PD
Power Dissipation
1
W
1
IOUT
Short-Circuit Output Current
50
mA
1



Description

TC59SM716AFT/AFTL is a CMOS synchronous dynamic random access memory organized as 2,097,152-words × 4 banks × 16 bits and TC59SMAFTL-70 is organized as 4,194,304 words × 4 banks × 8 bits and TC59SM704AFT/AFTL is organized as 8,388,608 words × 4 banks × 4 bits. Fully synchronous operations are referenced to the positive edges of clock input and can transfer data up to 143M words per second. These TC59SMAFTL-70 are controlled by commands setting. Each bank are kept active so that DRAM core sense amplifiers can be used as a cache. The refresh functions, either Auto Refresh or Self Refresh are easy to use. By having a programmable Mode Register, the system can choose the most suitable modes which will maximize its performance. These TC59SMAFTL-70 are ideal for main memory in applications such as work-stations.




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