TC6102

DescriptionThe TC6102 a two-port Switched Controller, is an ideal solution for dual speed Hub application. The chip supports a special backpressure with buffering feature (in half-duplex mode) for dual-speed Hub application. If the backpressure is enabled; when the stored packet count reached the ...

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TC6102: DescriptionThe TC6102 a two-port Switched Controller, is an ideal solution for dual speed Hub application. The chip supports a special backpressure with buffering feature (in half-duplex mode) for d...

floor Price/Ceiling Price

Part Number:
TC6102
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/26

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Product Details

Description



Description

The TC6102 a two-port Switched Controller, is an ideal solution for dual speed Hub application. The chip supports a special backpressure with buffering feature (in half-duplex mode) for dual-speed Hub application. If the backpressure is enabled; when the stored packet count reached the buffer threshold and the forwarding packet is detected at the same port, the TC6102 will send a JAM pattem on this port to stop receiving this packet. It means collision happened. If the successive collision count is too much, the TC6102 will let the forwarding packet come-in to prevent the Hub from partitioning. This special backpressure with buffering feature improves the communication quality and performance on dual-speed Hub application. It provides functions including filtering, forwarding, learning and aging between two 10/100 Mbps ports. It supports full auto-negotiation for capable PHYs. Therefore, The speed (10 or 100 Mbps) and duplex (half or full) which the PHY resolves to operate is automatically report to the TC6102. The chip in a system can recognize up to ZK different MAC addresses. An address recognition mechanism enables filtering and forwarding packets at full wire speed. It also implements address aging to update address table, addresses which have not been seen within 300 sec (or 20 sec) will be removed from the address table. The chip interfaces directly to 1 Mbyte(two 256Kx16) of EDO DRAM. The DRAM TC6102 is used to store the incoming/outgoing packets. The interface to EDO DRAM is glueless.

The features of TC6102 can be summarized as (1)single-chip, low cost, two port switched controller; (2)direct interface to two 10/100 Mbps MII (Media Independent Interface); (3)support half/full duplex(Full duplex for 10Mbps, Half duplex for 100Mbps); (4)support store and forward fragment-free switching approach; (5)support special backpressure with buffering feature for half-duplex operation; (6)support up to 2K MAC address; (7)automatic address aging at 300 seconds or 20 seconds; (8)forwarding and filtering at full wire speed(l488l0 packets/sec); (9)glueless interface to 1 Mbyte of EDO DRAM (two 256K*16); (10)low power CMOS design with single +5V supply; (11)100 pin PQFP package; (12).

The absolute maximum ratings of TC6102 are (1)supply voltage (VCC): -0.5V to 7.0V; (2)input voltage (DCIN): -0.5V to VCC + 0.5V; (3)output voltage (DCOUT): -0.5V to VCC + 0.5V; (4)storage temperature: -65°C to 150°C; (5)ESD protection: 2000V.




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