Features: • Bidirectional interface between 1.2-V and 1.8-V, 1.2-V and 2.5-V, 1.2-V and 3.3-V, 1.5-V and 2.5-V, 1.5-V and 3.3-V, 1.8-V and 2.5-V, 1.8-V and 3.3-V or 2.5-V and 3.3-V buses.
• High-speed operation: tpd = 6.8 ns (max) (VCCA = 2.5 ± 0.2 V, VCCB = 3.3 ± 0.3 V)
tpd = 8.9 ns (max) (VCCA = 1.8 ± 0.15 V, VCCB = 3.3 ± 0.3 V)
tpd = 10.3 ns (max) (VCCA = 1.5 ± 0.1 V, VCCB = 3.3 ± 0.3 V)
tpd = 61 ns (max) (VCCA = 1.2 ± 0.1 V, VCCB = 3.3 ± 0.3 V)
tpd = 9.5 ns (max) (VCCA = 1.8 ± 0.15 V, VCCB = 2.5 ± 0.2 V)
tpd = 10.8 ns (max) (VCCA = 1.5 ± 0.15 V, VCCB = 2.5 ± 0.2 V)
tpd = 60 ns (max) (VCCA = 1.2 ± 0.15 V, VCCB = 2.5 ± 0.2 V)
tpd = 58 ns (max) (VCCA = 1.2 ± 0.1 V, VCCB = 1.8 ± 0.15 V)
• Output current: IOH/IOL = ±12 mA (min) (VCC = 3.0 V)
IOH/IOL = ±9mA (min) (VCC = 2.3 V)
IOH/IOL = ±3 mA (min) (VCC = 1.65 V)
IOH/IOL = ±1mA (min) (VCC = 1.4 V)
• Latch-up performance: ±300 mA
• ESD performance: Machine model ±200 V
Human body model ±2000 V
• Ultra-small package: VSSOP (US16), VQON16
• Low current consumption: Using the new circuit significantly reduces current consumption when OE = "H".
Suitable for battery-driven applications such as PDAs and cellular phones.
• Floating A-bus and B-bus are permitted. (when OE = "H")
3.6-V tolerant function and power-down protection provided on all inputs and outputs.
Note 1: Do not apply a signal to any bus pins when it is in the output mode. Damage may result.
Note: When mounting VQON package, the type of recommended flux is RA or RMA.
Pinout
Specifications
| Characteristics |
Symbol |
Rating |
Unit |
| Power supply voltage (Note 2) |
VCCA
VCCB |
−0.5 to 4.6
−0.5 to 4.6 |
V |
DC input voltage
(DIR, OE ) |
VIN |
−0.5 to 4.6 |
V |
| DC bus I/O voltage |
VI/OA |
−0.5 to 4.6 (Note 3)
−0.5 to VCCA + 0.5 (Note 4) |
V |
| VI/OB |
−0.5 to 4.6 (Note 3)
−0.5 to VCCA + 0.5 (Note 4) |
|
Input diode current
Output diode current |
IIK
II/OK |
−50
±50 (Note 5) |
mA
mA |
| DC output current |
IOUTA
IOUTB |
±25
±25 |
mA |
| DC VCC/ground current per supply pin |
ICCA
ICCB |
±50
±50 |
mA |
Power dissipation
Storage temperature |
PD
Tstg |
180
−65 to 150 |
mW
|
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the ignificant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc).
Note 2: Don't supply a voltage to VCCB pin when VCCA is in the OFF state.
Note 3: Output in OFF state
Note 4: High or Low stats. IOUT absolute maximum rating must be observed.
Note 5: VOUT < GND, VOUT > VCC
DescriptionThe TC7MP3125FK/FTG is a dual supply, advanced high-speed CMOS 4-bit dual supply voltage interface bus ransceiver fabricated with silicon gate CMOS technology.
TC7MP3125FK is also designed with over voltage tolerant inputs and utputs up to 3.6 V.
Designed for use as an interface between a 1.2-V, 1.5-V, 1.8-V, or 2.5-V bus and a 1.8-V, 2.5-V or 3.6-V bus in mixed 1.2-V, 1.5-V, 1.8-V or 2.5-V/1.8-V, 2.5-V or 3.6-V supply systems.
The A-port interfaces with the 1.2-V, 1.5-V, 1.8-V or 2.5-V bus, the B-port with the 1.8-V, 2.5-V, 3.3-V bus.
The direction of data transmission is determined by the level of the DIR input. The enable input (OE) of TC7MP3125FK can be used to disable the device so that the buses are effectively isolated.
All inputs of TC7MP3125FK are equipped with protection circuits against static discharge or transient excess voltage.
TC7MP3125FK Data Sheet
