TC8830AF

The TC8830AF is a single chip CMOS LSI for voice recording/playback using the ADM(adaptive delta modulation).It composes a voice recording system  with a static RAM for voice memory and an audio circuit including a microphone, speaker, amplifier, etc, as an external circuit.

Features of the TC8830AF are:(1)SRAMs(static RAM)are used as a voice data memory up to 4 pieces of 64Kbit, or 4 pieces of 256Kbit; (2)it's possible to expanse atmemory up to smbitby external circuit; (3)it's connectable to microprocessor easily and controlled by 11 kinds of command; (4)capable of recording / playback maximum 16 phrases at the manual control; (5)4 kinds of bit rates ( 32K,16K,11K, SK bps)are provided; (6)recording / playback time is up to sixty four seconds(with four 256Iibit SRAMs and bit rate to be 16K bps ); (7)on-chip microphone amplifier for recording and band pass filter for playback; (8)it's possible to memory back up by standby function; (9)on-chip ceramic oscillation circuit; (10)single 5V power supply; (11)67-pin flat package.

The absolute maximum ratings of the TC8830AF can be summarized as:(1)supply voltage:-0.3 to 7.0V;(2)input voltage:-0.3 to Vdd+0.3V;(3)output voltage:-0.3 to Vdd+0.3V;(4)storage temperature:-55 to 125.Setting the P3 pin to L level results in the playback waiting state. When the PO pin is set at H level, the TC8830AF starts the playback after loading the start address and stop address, which have been written at the recording, into the address counter and stop address register, respectively.When the Pl pin is set at H level during the playback, the playback is paused.Playback is continued when the PO pin is set at H level under this condition.Setting the P3 pin to H level results in the recording waiting state. When the PO pin goes to H level(Startinput),the recording starts and the address counter is added successively. When the P1 is set at H level(Stop input ) or when the value on the address counter reaches the maximum address (Refer to section 5.5.6)of SRAMs by ADDRESS OVER FLOW DETECTOR(refer to section 5.6)the recording is stopped. Since this maximum address is changed with SRAMs capacity. Further, the recording is stopped when error address in the SRAM.