TH50VSF1480AASB

The TH50VSF1480AASB is a package of mixed 2,097,152-bit Full CMOS SRAM and 16,777,216-bit FLASH memory. The system can choose the mode which will maximize its performance with the CIOS/CIOF inputs. It operates 2.7 to 3.6 V power supply. It is available in a 65-pin BGA package to suit a variety of design applications.

There are some features of TH50VSF1480AASB as follows. First is data retention supply voltage which is from 1.5 to 3.6 V. The second is function mode control for FLASH compatible with JEDEC-standard command. Then is function mode of FLASH including auto program, auto chip erase, auto block erase, auto multiple block erase, block erase suspend, block erase resume, data polling and toggle bit. Next is erase and program cycle for FLASH which is 10⁵ cycles typical. The fifth is boot block architecture for FLASH which is top boot block.

What comes next is about the absolute maximum ratings of TH50VSF1480AASB. The VCC (power supply voltage) is from -0.3 to 4.6 V. The VIN (input voltage) is from -0.3 to 4.6 V. The VI/O (input/output voltage) is from -0.5 to VCC+0.5 V. The PD (power dissipation) is 0.6 W. The TSOLDER(soldering temperature (10 s)) is 260. The TSTG (storage temperature) is from -55 to 125. The TOPR (operating temperature) is from -20 to 85. The TOSHORT (output short circuit current) is 100 mA. The NEW (erase/program cycling capability) is 100,000 cycles.