TLIU04C1

The TLIU04C1 is a quad line interface containing four line transmit and receive channels for use in both North  American (T1/DS1) and European (E1/CEPT) applications. The line interface unit has the same functions as the Lucent T7698.

The TLIU04C1 can operate in either of two modes, chosen by the logic state of a control pin. A direct logic control mode provides the ability to define the architecture, initiate loopbacks, and monitor alarms without connecting to a microprocessor by setting the logic levels on control pins. The microprocessor mode uses a parallel microprocessor interface to allow the user to configure the device. The interface of TLIU04C1 is compatible with many commercially available microprocessors. The block diagrams of the microprocessor and direct logic modes are shown in Figure 2 and Figure 25, respectively.

The block diagram of the line interface unit is shown in Figure 3 on page 19 (it is repeated as Figure 26). The line receiver performs clock and data recovery using a fully integrated digital phase-locked loop. This digital implementation prevents false lock conditions that are common when recovering sparse data patterns with analog phase-locked loops.

Equalization circuitry in the receiver provides a high level of interference immunity. As an option, the raw sliced data (no retiming) can be output on the receive data pins. Transmit equalization is implemented with low-impedance output drivers that provide shaped waveforms to the transformer, guaranteeing template conformance. The TLIU04C1 will interface to the digital cross connect (DSX) at lengths of up to 655 ft. for DS1 operation or to line impedances of 75 Ω or 120 Ω for CEPT operation.

A selectable jitter attenuator may be placed in the receive signal path for low-bandwidth line-synchronous applications, or TLIU04C1 may be placed in the transmit path for multiplexer applications where DS1/CEPT signals are demultiplexed from higher rate signals. The jitter attenuator will perform the clock smoothing required on the resulting demultiplexed gapped clock.