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Part Number: TM8TU72JPW
Description: The TM8TU72JPW is a 64M-byte, 168-pin registered dual-in-line memory module (DIMM). The registered DIM...
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TM8TU72JPW
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General Description
TM8TU72JPW General Description
The TM8TU72JPW is a 64M-byte, 168-pin registered dual-in-line memory module (DIMM). The registered DIMM is composed of nine TMS664814DGE, 8 388 608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP); two SN74ALVC162836DGG, 20-bit universal bus drivers, each in a 240-mil, 56-pin thin shrink small-outline package (TSSOP); and one CDC2510 phase-lock loop (PLL) in a 177-mil, 24-pin TSSOP mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS695), the SN74ALVC162836 data sheet (literature number SCES129), and the CDC2510 data sheet (literature number SCAS597) for reference.
TM8TU72JPW Maximum Ratings
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 W
Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 150°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
TM8TU72JPW Features
` Organization: TM8TU72JPW . . . 8388608 * 72 Bits
` Designed for 100-MHz, 72-Bit 4-Clock Systems
` JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) With Register for Use With Socket
` TM8TU72JPW - Uses Nine 64M-Bit (8M * 8-Bit) SDRAMs in Plastic Thin Small-Outline Package (TSOP), Two SN74ALVC162836 20-Bit Universal Bus Drivers in Thin Shrink Small-Outline Package (TSSOP), and One CDC2510 Phase-Lock Loop (PLL) in TSSOP
` Single 3.3-V Power Supply (±10% Tolerance)
` Performance Ranges:
` Byte-Read/Write Capability
` High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface
` Read Latencies 2 and 3 Supported
` Supports Burst-Interleave and Burst-Interrupt Operations
` Burst Length Programmable to 1, 2, 4, and 8
` Four Banks for On-Chip Interleaving (Gapless Access)
` Ambient Temperature Range 0°C to 70°C
` Gold-Plated Contacts
` Pipeline Architecture
` Serial Presence-Detect (SPD) Using EEPROM
` Designed for 100-MHz, 72-Bit 4-Clock Systems
` JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) With Register for Use With Socket
` TM8TU72JPW - Uses Nine 64M-Bit (8M * 8-Bit) SDRAMs in Plastic Thin Small-Outline Package (TSOP), Two SN74ALVC162836 20-Bit Universal Bus Drivers in Thin Shrink Small-Outline Package (TSSOP), and One CDC2510 Phase-Lock Loop (PLL) in TSSOP
` Single 3.3-V Power Supply (±10% Tolerance)
` Performance Ranges:
` Byte-Read/Write Capability
` High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface
` Read Latencies 2 and 3 Supported
` Supports Burst-Interleave and Burst-Interrupt Operations
` Burst Length Programmable to 1, 2, 4, and 8
` Four Banks for On-Chip Interleaving (Gapless Access)
` Ambient Temperature Range 0°C to 70°C
` Gold-Plated Contacts
` Pipeline Architecture
` Serial Presence-Detect (SPD) Using EEPROM
TM8TU72JPW
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- Datasheet: TM8TU72JPW
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