Features: ` Highest Performance Fixed-Point Digital Signal Processor (DSP) TMS320C6201
6-, 5-ns Instruction Cycle Time
167-, 200-MHz Clock Rate
Eight 32-Bit Instructions/Cycle
1336, 1600 MIPS
` Highest Performance Fixed-Point Digital Signal Processor (DSP) TMS320C6201B
5-, 4.3-ns Instruction Cycle Time
200-, and 233-MHz Clock Rates
Eight 32-Bit Instructions/Cycle
1600, 1860 MIPS
` VelociTIE Advanced Very Long Instruction Word (VLIW) 'C62x CPU Core
Eight Independent Functional Units:
Six ALUs (32-/40-Bit)
Two 16-Bit Multipliers (32-Bit Results)
Load-Store Architecture With 32 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
` Instruction Set Features
Byte-Addressable (8-, 16-, 32-Bit Data)
32-Bit Address Range
8-Bit Overflow Protection
Saturation
Bit-Field Extract, Set, Clear
Bit-Counting
Normalization
` 1M-Bit On-Chip SRAM
512K-Bit Internal Program/Cache (1K 32-Bit Instructions)
512K-Bit Dual-Access Internal Data (64K Bytes) Organized as a Single Block ('6201)
512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency ('6201B)
` 32-Bit External Memory Interface (EMIF)
Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
Glueless Interface to Asynchronous Memories: SRAM and EPROM
` Four-Channel Bootloading Direct-Memory-Access (DMA) Controller with an Auxiliary Channel
` 16-Bit Host-Port Interface (HPI)
Access to Entire Memory Map
` Two Multichannel Buffered Serial Ports (McBSPs)
Direct Interface to T1/E1, MVIP, SCSA Framers
ST-Bus-Switching Compatible
Up to 256 Channels Each
AC97-Compatible
Serial Peripheral Interface (SPI) Compatible (MotorolaE)
` Two 32-Bit General-Purpose Timers
` Flexible Phase-Locked Loop (PLL) Clock Generator
` IEEE-1149.1 (JTAG†) Boundary-Scan Compatible
` 352-Pin BGA Package (GGP Suffix) ('6201)
` 352-Pin BGA Package (GJC Suffix) ('6201B)
` 352-Pin BGA Package (GJL Suffix) ('6201B)
` CMOS Technology
0.25-mm/5-Level Metal Process ('6201)
0.18-mm/5-Level Metal Process ('6201B)
` 3.3-V I/Os, 2.5-V Internal ('6201)
` 3.3-V I/Os, 1.8-V Internal ('6201B)SpecificationsSupply voltage range, CVDD (see Note 1) for 'C6201 . . . . . .0.3 V to 3 V
Supply voltage range, CVDD (see Note 1) for 'C6201B . . . 0.3 V to 2.3 V
Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . 0.3 V to 4 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V
Operating case temperature range TC: (default) . . . . . . . . . .0 to 90
(A version) . . .. . . . .40 to 105
Storage temperature range, Tstg .. . . . . . . . . . . . . .. . . . . 55 to 150
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
DescriptionThe TMS320C62x† DSPs (including the TMS320C6201 and the TMS320C6201B devices) are the fixed-point DSP family in the TMS320C6000 platform. The TMS320C6201 ('C6201) and the TMS320C6201B ('C6201B) devices are based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TIE), making these DSPs an excellent choice for multichannel and multifunction applications. With performance of up to 1600 million instructions per second (MIPS) at a clock rate of 200 MHz, the 'C6201 offers cost-effective solutions to high-performance DSP programming challenges. The 'C6201B is a newer revision of the 'C6201 with performance of up to 1860 MIPS at a clock rate of 233 MHz. The 'C6201/'C6201B DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. Each of these processors have 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. Both the 'C6201 and the 'C6201B can produce two multiply-accumulates (MACs) per cycle-for a total of 400 million MACs per second (MMACS) for the 'C6201, and a total of 466 MMACS for the 'C6201B. The 'C62x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
The 'C6201/'C6201B includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory of the 'C6201 consists of a 64K-byte block of RAM, while data memory of the 'C6201B consists of two 32K-byte blocks of RAM for improved concurrency. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.
The 'C62x has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a WindowsE debugger interface for visibility into source code execution.
TMS320C6201 Data Sheet
