TP3054

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
V_CC to GNDA .........................7V
V_BB to GNDA......................... -7V
Voltage at any Analog Input
or Output ................V_CC-0.3V to V_BB+ 0.3V
Voltage at any Digital Input or
Output .................V_CC+0.3V to GNDA-0.3V
Operating Temperature Range .......-25°C to+ 125°C
Storage Temperature Range ........-65°C to +150°C
Lead Temperature (Soldering, 10 seconds) .......300°C
ESD (Human Body Model)................ 2000V
Latch-Up Immunity =100 mA on any Pin

The TP3054, TP3057 family consists of -law and A-law monolithic PCM CODEC/filters utilizing the A/D and D/A conversion architecture shown inFigure 1 , and a serial PCM interface. The TP3054, TP3057 devices are fabricated using National's advanced double-poly CMOS process (microCMOS).

The encode portion of each TP3054, TP3057 device consists of an input gain adjust amplifier, an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz. Also included are auto-zero circuitry and a companding coder which samples the filtered signal and encodes it in the companded -law or A-law PCM format. The decode portion of each device consists of an expanding decoder, which reconstructs the analog signal from the companded m-law or A-law code, a low-pass filter whichcorrects for the sin x/x response of the decoder output and rejects signals above 3400 Hz followed by a single-ended power amplifier capable of driving low impedance loads. The devices require two 1.536 MHz, 1.544 MHz or 2.048 MHz transmit and receive master clocks, which may be asynchronous; transmit and receive bit clocks, which may vary from 64 kHz to 2.048 MHz; and transmit and receive frame sync pulses. The timing of the frame sync pulses and PCM data is compatible with both industry standard formats.