U6055B

The U6055B has the following features including 8/16 bit parallel-serial-parallel conversion;Only a single data line is necessary;Quadruple comparison of the data signal for high transmission safety;Minimum of peripherals;All output memories are reset if data line is disturbed;Disturbed data line is displayed;Transmitter and receiver prepared for master/slave operation;Transmitter data output short circuit protected;Transmitter can be powered via data line;Wide suppfyvoltage range;Meet the demands of VDE regulation 0839;Load dump protected.

The data word of U6055B consists of 2 start bits and 8 information units. For a transmitter frequency of 6.4 kHz, the data word length is 5 ms plus the start pulse, followed by a 10 ms long data interval. The data interval has high potential. When the supply voltage is applied, data transmission is constantly repeated in accordance with this pattern (Fig. 3).After the supply voltage Vbatt is applied to the transmitter, a POWER-OH-RESET pulse (POR) is generated internally which sets the logic of the U 6055 B to a basic condition. In contrast to the U60508, the data output (s not disabled at the start and is thus immediately ready for operation.The U60558 is normallyoperatedwitha stabilized voltage in conjunction with a microprocessor.Loading of the shift register is controlled in the known way by the three inputs DIN, CLK and EN. Nodata can be inserted intheshift register with EN="low".IfEN="high",theinformationfromthe microprocessor present at the data input DIN is transferred to the shift register with the positive edge of CLK and advanced by one position with every further positive edge from CLK. The eighth flip-flop is a master-slave flip-flop: the information of the eighth flipflop is transferred to the slave with every negative edge from CLK and is available at the output DOUT.

After coincidence U6055B has been established two or four times (programmable pin 2/4), the contents of the buffer are compared with the contents of the output memory.If both are identical,the 4 stage counter is reset and no new information istransferred to the output  memory.  If the contents  of the two memories differ, the data of U6055B word musf have changed and is transferred into the output memory. Since the period of a data transmission is 15 ms, this results in a minimum delay time of 60 ms resp. 30 ms for detection of a change of the data word. Faults on the data line and switch bouncing may lead to an extension of the delay time.