UA1E

The UA1E series of ULCs is well suited for conversion of large sized CPLDs and FPGAs. We can support within one ULC from 18 Kbits to 390 Kbits DPRAM and from 46 Kgates to 780 Kgates. Typically, ULC die size is 50% smaller than the equivalent FPGA die size. DPRAM blocks are compatible with Xilinx or Altera FPGA blocks.

UA1E series are implemented in highperformance CMOS technology with 0.35m (drawn) channel lengths, and are capable of supporting flipflop toggle rates of 200 MHz at 3.3V and 180 MHz at 2.5V, and input to output delays as fast as 150ps at 3.3V. The architecture of the UA1E series allows for efficient conversion of many PLD architecture and FPGA device types with higher IO count. A compact RAM cell, along with the large number of available gates allows the implementation of RAM in FPGA architectures that support this feature, as well as JTAG boundaryscan and scanpath testing.

Conversion to the UA1E series of ULC can provide a significant reduction in operating power when compared to the original PLD or FPGA. This is especially true when compared to many PLD and CPLD architecture devices, which typically consume 100mA or more even when not being clocked. The UA1E series has a very low standby consumption of 0.3nA/gate typically commercial temperature, which would yield a standby current of 42A on a 144,000 gates design. Operating consumption is a strict function of clock frequency, which typically results in a power reduction of 50% to 90% depending on the UA1E series being compared.

The UA1E series provides several options for output buffers, including a variety of drive levels up to 18mA. Schmitt trigger inputs are also an option. A number of techniques are used for improved noise immunity and reduced EMC emissions, UA1E series including: several independent power supply busses and internal decoupling for isolation; slew rate limited outputs are also available if required.

The UA1E series is designed to allow conversion of high performance 3.3V devices as well as 2.5V devices. Support of mixed supply conversions is also possible, allowing optimal tradeoffs between speed and power consumption.