UG140

The UG series of ULCs is well suited for conversion of medium- to-large sized CPLDs and FPGAs. Devices are implemented in high-performance CMOS technology with 0.6-m (drawn) channel lengths, and are capable of supporting flip-flop toggle rates of 350 MHz, operating clock frequencies up to 150 MHz and input to output delays as fast as 5 ns.

The architecture of the UG series allows for efficient conversion of many PLD architectures and FPGA device types. A compact RAM cell, along with the large number of available gates allows the implementation of RAM in FPGA architectures that support this feature, as well as JTAG boundary-scan and scan-path testing.

Conversion to the UG series of ULC can provide a significant reduction in operating power when compared to the original PLD or FPGA. This is especially true when compared to many PLD and CPLD architecture devices, which typically consume 100 mA or more even when not being clocked. The UG series has a very low standby consumption of 0.4 nA/gate typically, which would yield a standby current of 4 mA on a 10,000 gate design. Operating consumption is a strict function of clock frequency, which typically results in a power reduction of 50% to 90% depending on the device being compared.

The UG series provides several options for output buffers, including a variety of drive levels up to 24 mA. Schmitt trigger inputs are also an option. A number of techniques are used for improved noise immunity and reduced EMC emissions, including: several independent power supply busses and internal decoupling for isolation; slew rate limited outputs are also available as required.

The UG series is designed to allow conversions of high performance 3.3V devices as well as 5.0V devices. Support of mixed supply conversions is also possible, allowing optimal trade-offs between speed and power consumption.