UG222

High performance ULC family suitable formedium- to large-sized CPLDs and FPGAs
Conversions to over 700,000 FPGA gates
Pin counts to over 582 pins
Any pin-out matched due to limited number ofdedicated pads
Full range of packages: DIP, SOIC, LCC/PLCC,PQFP/TQFP, PGA/PPGA, PBGA/CABGA
3.3V and/or 5.0V operation.
Low quiescent current: 0.04 nA/gate
Available in commercial, industrial, automotive,military and space grades.
0.5 µm Drawn CMOS, 3 Metal Layers
Library Optimised for Synthesis, Floor Plan &Automatic Test Generation (ATG)
High Speed Performances: 200 ps Typical Gate Delay @5 V Typical 625 MHz Toggle Frequency @5Vand 360 MHz @3.3 V
High System Frequency Skew Control: Clock Tree Synthesis Software
3 & 5 Volts Operation; Single or Dual SupplyModes
Low Power Consumption: 0.6 µW/Gate/MHz @3 V 2.2 µW/Gate/MHz @5 V
Power on Reset
Standard 3, 6, 12 and 24mA I/Os
CMOS/TTL/PCI Interface
ESD (2 kV) and Latchup Protected I/O
High Noise & EMC Immunity: I/O with Slew Rate Control Internal Decoupling Signal Filtering between Periphery & Core Application DependentSupply Routing &Several

The UG2 series of ULCs is well suited for conversion ofmedium- to-large sized CPLDs  and FPGAs. Devices areimplemented in high-performance CMOS technologywith 0.5-µm (drawn) channel lengths, and are capable ofSupporting flip-flop toggle rates of 625 MHz at 5V and360 MHz at 3.3V, operating clock frequencies up to 150MHz and input to output delays as fast as 5 ns, 200 ps at5V.

The architecture of the UG2 series allows for efficientconversion of many PLD architecture and FPGA devicetypes with higher IO count. A compact RAM cell, alongwith the large number of available gates allows theimplementation of RAM in FPGA architectures thatsupport this feature, as well as JTAG boundary-scan andscan-path testing.

Conversion to the UG2 series of ULC can provide asignificant reduction in operating power whencompared to the original PLD or FPGA.  This  isespecially true when compared to many PLD and CPLDarchitecture devices, which typically consume 100 mAor more even when not being clocked.  The UG2 serieshas a very low standby consumption of 0.4 nA/gatetypically commercial temp, which would yield astandby current of 0.4 nA/gate, 4 mA on a 10,000 gatedesign. 

Operating consumption is a strict function ofclock frequency, which typically results in a powerreduction of 50% to 90% depending on the device beingcompared.

The UG2 series provides several options for outputbuffers,  including a variety of drive levels up to 24 mA.Schmitt trigger inputs are also an option. A number oftechniques are used for improved noise immunity andreduced EMC emissions, including: severalindependent power supply busses and internaldecoupling for isolation; slew rate limited outputs arealso available as required.

The UG2 series is designed to allow conversions of highperformance 3-V devices as well as 5-V devices.Support of mixed supply conversions is also possible,allowing optimal trade-offs between speed and powerconsumption.