UPC4072

The UPC4072 is a low power J-FET input operational amplifier that is designed as low low noise version of the UPC4082. The feature of UPC4072 are as follows: (1)very low input bias and offset currents; (2)output short circuit protection; (3)high input impedance: J-FET input stage; (4)internal frequency compensation; (5)high slew rate: 13V/s.

The absolute maximum ratings of the UPC4072 are: (1)voltage between V+ and V-: -0.3 to +36V; (2)differential input voltage: ±30V; (3)input voltage: V-0.3 to V+0.3V; (4)output voltage: V-0.3 to V+0.3V; (5)power dissipation: 350mW; (6)output short circuit duration: indefinite sec; (7)operating temperature range: -20 to +80; (8)storage temperature range: -55 to +125.

The following is about the electrical characteristics of UPC4072: (1)input offset voltage: ±3 mV typical and ±10 mV max at Rs50; (2)input offset current: ±5 pA typical and ±50 pA max; (3)input bias current: 30 pA typical and 200 pA max; (4)large signal voltage gain: 25V/mV min, 200V/mV typical at Rs2k, Vo=±10V; (5)supply current: 4mA typical and 5mA max at Io=0A, both amplifiers; (6)common mode rejection ratio: 70dB min, 86dB typical; (7)supply voltage rejection ratio: 70dB min, 86dB typical; (8)unity gain frequency: 3MHz; (9)channel separation: 120dB.