Purchase UPD720100AGM-8EY, In-stock UPD720100AGM-8EY From SeekIC.
MFG:NEC Package Cooled:TQFP D/C:08+
- Table of contents:
UPD720100AGM-8EY
-
Suppliers
DataSheet
General Description
UPD720100AGM-8EY Features
• Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)
• Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
• Compliant with Enhanced Host Controller Interface Specification for USB Rev 0.95
• PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI host controller core for high-speed signaling.
• Root hub with five (max.) downstream facing ports which are shared by OHCI and EHCI host controller core
• All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps)
transaction.
• Configurable number of downstream facing ports (2 to 5)
• 32-bit 33 MHz host interface compliant to PCI Specification release 2.2.
• Supports PCI Mobile Design Guide Revision 1.1.
• Supports PCI-Bus Power Management Interface Specification release 1.1.
• PCI Bus bus-master access
• System clock is generated by 30 MHz X'tal or 48 MHz clock input.
• Operational registers direct-mapped to PCI memory space
• Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard
implementation.
• 3.3 V power supply, PCI signal pins have 5 V tolerant circuit.
• Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
• Compliant with Enhanced Host Controller Interface Specification for USB Rev 0.95
• PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI host controller core for high-speed signaling.
• Root hub with five (max.) downstream facing ports which are shared by OHCI and EHCI host controller core
• All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps)
transaction.
• Configurable number of downstream facing ports (2 to 5)
• 32-bit 33 MHz host interface compliant to PCI Specification release 2.2.
• Supports PCI Mobile Design Guide Revision 1.1.
• Supports PCI-Bus Power Management Interface Specification release 1.1.
• PCI Bus bus-master access
• System clock is generated by 30 MHz X'tal or 48 MHz clock input.
• Operational registers direct-mapped to PCI memory space
• Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard
implementation.
• 3.3 V power supply, PCI signal pins have 5 V tolerant circuit.
UPD720100AGM-8EY Connection Diagram
UPD720100AGM-8EY
PDF/DataSheet Download
- Datasheet: UPD720100AGM-8EY
- File Size: 312096 KB
- Manufacturer: NEC [NEC]
- Click here to Download
- ·UPD100500D-15
- x1 SRAM
- 101698 KB
- ·UPD100500D-20
- x1 SRAM
- 101698 KB
- ·UPD100504D-15
- x4 SRAM
- 101162 KB
- ·UPD10500D-15
- x1 SRAM
- 108645 KB
- ·UPD10500D-20
- x1 SRAM
- 108645 KB
- ·UPD10504D-15
- x4 SRAM
- 107973 KB
- ·UPD120N
- NEC [NEC]
- THREE-TERMINAL LOW-DROPOUT POSITIVE-VOLTAGE REGULATOR (OUTPUT CURRENT: 0.3 A)
- 161162 KB
- ·UPD120N15T1B
- NEC [NEC]
- THREE-TERMINAL LOW-DROPOUT POSITIVE-VOLTAGE REGULATOR (OUTPUT CURRENT: 0.3 A)
- 161162 KB
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