V103

• Pin compatible with THine THC63LVD103
• Wide pixel clock range: 8 - 135 MHz
• Supports a wide range of video and graphics modes including VGA, SVGA, XGA, SXGA, SXGA+, NTSC, PAL, SDTV, and HDTV up to 1080I or 720P
• Internal PLL requires no external loop filter
• Selectable rising or falling clock edge for data alignment
• Compatible with Spread Spectrum clock source
• Reduced LVDS output voltage swing mode (selectable) to minimize EMI
• CMOS/TTL data inputs can be configured for reduced input voltage swing
• Single 3.3 V supply
• Low power consumption CMOS design
• Power down mode
• 64-pin TQFP lead free package

Stresses above the ratings listed below can cause permanent damage to the V103. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range
Supply Voltage, V_CC ...........................-0.3 V to +4.0 V
CMOS/TTL Input Voltage ..............-0.3 V to V_CC+0.3 V
CMOS/TTL Output Voltage........... -0.3 V to V_CC+0.3 V
LVDS Driver Output Voltage........ -0.3 V to V_CC+0.3 V
Storage Temperature........................... -55 to +150
Junction Temperature .......................................120
Soldering Temperature (10 seconds)............... 260
Maximum Power Dissipation @ 25 .................1.0 W

The V103 LVDS display interface transmitter is primarily designed to support pixel data transmission between a video processing engine and a digital video display. The data rate supports up to SXGA+ resolutions and can be used in Plasma, Rear Projector, Front Projector, CRT and LCD display applications. It can also be used in other high-bandwidth parallel data applications and provides a low EMI interconnect over a low cost, low bus width cable up to several meters in length.
 
The V103 converts 35 bits of CMOS/TTL data, clocked on the rising or falling edge of an input clock (selectable), into six LVDS (Low Voltage Differential Signaling) serial data stream pairs. In video applications the 35 bits is normally divided into 10 bits for each R, G and B channel and 5 control bits.

When combined with the V104 LVDS display interface receiver, the V103 + V104 combination provides a 35-bit wide, 90 MHz transport. The rate of each LVDS channel is 630 Mbps for a 90MHz data input clock, 945 Mbps for 135MHz.