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V104

Features: • Pin & function compatible with the THC63LVD104A• Wide pixel clock range: 8 - 90 MHz• Supports resolutions from 480p to WXGA• Internal PLL does not require external loop filter• Clock edge selection for TTL alignment selectable• Power down mode...

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SeekIC No. : 004539504 Detail

V104: Features: • Pin & function compatible with the THC63LVD104A• Wide pixel clock range: 8 - 90 MHz• Supports resolutions from 480p to WXGA• Internal PLL does not require ext...

V104 Data Sheet

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Part Number:
V104
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/25

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Product Details

Description



Features:

• Pin & function compatible with the THC63LVD104A
• Wide pixel clock range: 8 - 90 MHz
• Supports resolutions from 480p to WXGA
• Internal PLL does not require external loop filter
• Clock edge selection for TTL alignment selectable
• Power down mode
• Single 3.3V supply
• Low power consumption CMOS design
• 64-pin TQFP lead free package


Pinout

Connection Diagram


Specifications

Item Rating
Supply Voltage, VCC -0.3 V to +4.0 V
CMOS/TTL Input Voltage -0.3 V to VCC+0.3 V
CMOS/TTL Output Voltage -0.3 V to VCC+0.3 V
LVDS Receiver Input Voltage -0.3 V to VCC+0.3 V
Output Current -30 mA to 30 mA
Storage Temperature -55 to +125
Junction Temperature 125
Soldering Temperature (10 seconds) 260
Maximum Power Dissipation @ +25 1.0 W




Description

The V104 10 Bit LVDS Receiver for Video is designed to support video data transmission between display engines and video processing engines for television and projector applications. The V104 supports up to WXGA resolutions for Plasma, Rear Projection, Front Projection, CRT and LCD applications.

The V104 converts the 6 LVDS (Low Voltage Differential Signaling) video data stream pairs to 35 CMOS/TTL data bits with a rising or falling edge clock. The clock edge selection is performed using a dedicated pin.

In conjunction with the V103 transmitter, the V104 can transmit 10 bits per color (R, G, B) along with 5 bits of control and timing data (HSYNC, VSYNC, DE, CNTL1, CNTL2) over a low EMI, low bus width connection including connectors and standard LVDS cabling.




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