VG3617161BT

The VG3617161BT is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V power supply and which is CMOS synchronous dynamic RAM organized as 524,288-word X 16-bit X 2-bank. VG3617161BT is packaged by using JEDEC standard pinouts and standard plastic 50-pin TSOP II. This SDRAM is delicately designed with performance concern for current high-speed application. Programmable CAS Latency and Burst Length make it possible to be used in widely various domains.

The features of VG3617161BT can be summarized as (1)single 3.3V +/- 0.3V power supply; (2)clock frequency: 200MHz, 183MHz, 166MHz, 143MHz, 125MHz; (3)fully synchronous with all signals referenced to a positive clock edge; (4)programmable CAS Iatency (2,3); (5)programmable burst length (1,2,4,8,& Full page); (6)programmable wrap sequence (Sequential/Interleave); (7)automatic precharge and controlled precharge; (8)auto refresh and self refresh modes; (9)dual internal banks controlled by A11(Bank select); (10)simultaneous and independent two bank operation; (11)I/O level : LVTTL interface; (12)random column access in every cycle; (13)X16 organization; (14)byte control by LDQM and UDQM; (15)2048 refresh cycles/32ms; (16)burst termination by burst stop and precharge command.

The absolute maximum ratings of VG3617161BT are (1)voltage on any pin relative to Vss VIN,VOUT: -1.0 to +4.6 V; (2)supply voltage relative to Vss VDD,VDDQ: -1.0 to +4.6 V; (3)short circuit output current IOUT: 50 mA; (4)power dissipation PD :1.0 W; (5)operating temperature TOPT: 0 to + 70°C; (6)storage temperature TSTG: -55 to + 125°C.